1. Field of the Invention
This invention relates to an ATM communication system. More particularly, the invention relates to a system and method for an efficient adapter/device driver interface in an ATM system.
2. Description of the Prior Art
Asynchronous transmission mode (ATM) systems are unique in that they can transmit many frames simultaneously by dividing each frame into 48 bytes segments, appending a 5 byte header to each segment, and transmitting the resulting 53 byte cell multiplexed with cells from other frames which are queued for transmission. When cells are received, they are reassembled into frames by stripping the 5 byte cell header and concatenating the remaining 48 bytes with previously received cells for that frame. Different frames may be in various stages of segmentation and reassembly at any given time.
Typically in an ATM system, whenever you want to transmit frames, a device driver has to set up transmit commands to an adapter which transmits the frames and produces an interrupt back to the device driver indicating that the transmit operation is complete. The same general process occurs in the receive direction, that is the device driver issues commands and the adapter, after receiving the data, interrupts the device driver indicating the receive operation is complete. As the data rate increases on the ATM network, the frequency at which the device driver issues the commands and processes the interrupts increases to the point that the device driver can no longer keep up with the data rate. Also, the slowing of the device driver with respect to the data rate increases storage requirements in the adapter and system memory. A system and method which reduces the activity of the device driver in transmitting and receiving data will enhance the performance of ATM systems. More specifically, a system and method which simultaneously segments frames into cells and reassembles cells into frames independent of a system or a device driver across an adapter/driver interface will improve performance and lower storage requirements for the ATM system.
In the related prior art, U.S. Pat. No. 5,297,139 issued Mar. 22, 1994, discloses a method of controlling writing of data from a communication transmission line into a buffer device and reading of the data out of the buffer device. The data is read out of a buffer at a predetermined read rate and the quantity of data written in said buffer is compared with a predetermined threshold. The data from the transmission line is written into the buffer device when it is found that the quantity of accumulated data is the same as or less than the threshold, the buffer performs only write of data from the transmission line. The buffer performs both write of data from the communication transmission line and reading of data out of the buffer device when the quantity of the accumulate data is larger than the threshold.
U.S. Pat. No. 5,274,768 issued Dec. 28, 1993, discloses an interface for coupling a computer to a telecommunication network. The interface includes reassembler for receiving and reassembling frames segmented into a plurality of ATM's cells, each of which comprises a virtual channel identifier and a cell body. The reassembler further includes means for separating each cell body from the associated virtual channel identifier and determining respective link list reference addresses for the virtual channel identifier. A reassembly buffer stores the cell bodies; and a link list manager stores link list data indicative of addresses in which the cell bodies are stored in the reassembly buffer means.
U.S. Pat. No. 5,136,584 issued Aug. 4, 1992 discloses an interface to a multiplexed high speed digital communication network. The interface includes an input port for receiving data (illustratively ATM cells), an output port for transmitting processed received data and a data delay arrangement (illustratively a delay pipeline) that interconnects the input port with the output port and delays propagation of received data in order to provide time for processing the data. The interface uses no internal data storage but makes use of the delay pipeline to move data through the interface as rapidly as possible. A data assembler and state memory assemble data frames out of the received multiplexed, interleaved ATM cells.
None of the prior art addresses the problem of an ATM adapter/device driver interface in segmenting multiple frames from different data sources into cells for transmission and reassembling cells into multiple frames for reception to an application, the transmission and reassembling essentially independent of the device driver. As a result, the device driver is able to keep up with network data rates which improves the performance of ATM system in handling high speed data rates and reduces storage usage at the interface. Nor does the prior art disclose the use of frame descriptors and lists for locating frames in system memory without the use of partitions. Nor does the prior art disclose the use of pointers for linking frames together in transmit ready queues and receive ready lists.